1. Field of the Invention
This circuit relates in general to an electronic circuit and in particular to transient detection for an electronic circuit.
2. Description of the Related Art
An integrated circuit may be subjected to an Electrostatic Discharge (ESD) event during its manufacture, assembly, or testing, or during its ultimate system application. In conventional integrated circuit (IC) ESD protection schemes, special clamp circuits are often used to shunt ESD currents between the IC power supply rails and thereby protect sensitive internal circuitry from damage. A type of ESD clamp circuit, known as an active Metal Oxide Semiconductor Field Effect Transistor (MOSFET) clamp circuit, may contain three functional elements; a transient detection circuit, an on time control circuit, and a clamp switch which may include a large MOSFET. The transient detection circuit is designed to respond to the rapid rise time characteristic of an ESD event, typically 100 picoseconds to 60 nanoseconds, but remain inactive during normal operation of the IC. The on-time control circuit may be used to amplify the transient detection circuit output in order to fully turn on the large MOSFET into a low resistance conducting state. The on-time control circuit may also be used to hold the large MOSFET in this low resistance conducting state for a period of time, which typically exceeds the maximum expected duration of an ESD event, which is typically 500–1000 nanoseconds. The MOSFET connected between the two power supply rails acts as the primary ESD current dissipation device in the clamp circuit. Since the peak current in an ESD event is typically on the order of amperes, MOSFETs with channel widths of thousand of microns are typically used in order to achieve the desired low on-resistance between the two power supply rails.
FIG. 1 is a circuit diagram of a prior art ESD clamp circuit. The clamp circuit 101 protects a VDD power supply rail connected to node 102 from positive ESD events referenced to a grounded VSS power supply rail connected to node 103. Clamp circuit 101 includes a transient detection circuit 105, an on-time control circuit 107, and a clamp switch 106. Clamp switch 106 is shown configured as a large N-channel MOSFET, or NMOS transistor, with its source connected to node 103 and its drain connected to node 102. Alternate clamp circuit designs may utilize other types of switches such as, e.g., a P-channel MOSFET, or PMOS transistor, as the clamp switch.
FIG. 2 is a diagram showing the operation of transient detection circuit 105 in response to a simulated ESD event applied to the power supply rail (VDD) connected to node 102 with node 103 grounded. The simulated ESD event induces on node 102 a linear voltage ramp from 0 volts (V) to 4V, with a rise time of 60 nanoseconds (ns). While a typical ESD event will not produce the perfectly linear voltage ramp on node 102 as shown in FIG. 2, the linear ramp is very useful for characterizing the transient response of transient detection circuit 105. Resistor 109 and capacitor 111 form a resistor-capacitor (RC) filter, such that node 110 will rise from 0 V towards the voltage of node 102 with a characteristic delay time controlled by the RC time constant for the filter. The RC time constant is the product of the resistance of resistor 109 and capacitance of capacitor 111. As shown in FIG. 2, during the rise time of node 102, node 110 asymptotically approaches, but for this brief rise time does not quite reach, a slew rate (slope) matching the slew rate of node 102. It can be shown that, when the slew rates for these two nodes match, the horizontal offset between node 102 and node 110 just equals the RC time constant for the filter. In the example shown in FIG. 1, the RC time constant is about 44 ns. This is less than the 60 ns rise time of node 102.
As shown in FIG. 1, node 110 serves as the input to an inverter circuit 113. Inverter circuit 113 may be a conventional CMOS inverter circuit consisting of an NMOS and a PMOS transistor in series (not shown) with their source terminals connected to nodes 103 and 102 respectively, and with their gate terminals connected to node 110. The drain terminals of both transistors are connected to node 112. In the following description, a “high” signal refers to a voltage level at or near the voltage level of node 102, whereas a “low” signal refers to a voltage level at or near the voltage of node 103 This nomenclature is used, for example, to indicate switching states of an inverter circuit. The voltage switch point of inverter circuit 113 is the input voltage threshold at which its output changes states. As can be seen in FIG. 2, the voltage switch point of inverter circuit 113, as shown by the dashed line labeled “voltage switch point of inverter circuit 113,” is a constant fraction of the instantaneous voltage on node 102. With the circuit of FIG. 1, the NMOS and PMOS transistors in inverter circuit 113 are sized in the most common manner, so that the voltage switch point equals approximately one-half the instantaneous voltage on node 102.
The maximum ESD rise time is defined as the longest possible rise time of an ESD event that transient detection circuit 105 should properly detect. In the present example, this maximum ESD rise time is assumed equal to 60 ns, which is the rise time of node 102 shown in FIG. 2. While a maximum ESD rise time of 60 ns is assumed in the present example, other maximum ESD rise times (e.g. 20 ns) may be used depending on expected ESD rise time characteristics. With the circuit of FIG. 1, the RC time constant of transient detection circuit 105 has been intentionally adjusted so that the voltage at node 110 remains below the inverter circuit 113 voltage switch point for the full 60 ns. This can be seen in FIG. 2, where node 110 rises above the voltage switch point of inverter circuit 113 just at the end of the 60 ns rise time of node 102. The output of inverter circuit 113 (node 112) tracks node 102 (output high) for a portion of the rise time of node 102, only dropping to near VSS (output low) as the inverter circuit switches states at the 60 ns point. Note that, at the very beginning of the node 102 ramp, the output of inverter circuit 113 is not driven high until node 102 reaches about 0.65V. This is due to the fact that the inverter circuit functions in a weak conduction mode until node 102, which also serves as the power supply for inverter circuit 113, reaches the threshold voltage for the PMOS transistor in inverter circuit 113. During that time, the output impedance of inverter circuit 113 is very high and the voltage at its output node 112 is mainly determined by the parasitic capacitances connected to node 112.
The operation of on-time control circuit 107 in FIG. 1 can be described as follows. An ESD event detected by transient detection circuit 105 should produce a high signal at node 112 for the full rise time of the ESD event. With a high signal at node 112, inverter circuit 115 drives the gate of PMOS transistor 117 low. This turns on PMOS transistor 117 which then pulls node 118 up to node 102 (high), fully turning on the large NMOS transistor 106. NMOS transistor 106 serves as the primary ESD current shunting device between node 102 and node 103. At the end of the voltage ramp on node 102, the output of transient detection circuit 105 (node 112) switches low and the output of inverter circuit 115 switches high. This makes PMOS transistor 117 nonconductive. Beyond this point in time, the voltage at node 118 will exponentially decay towards voltage of node 103 with an RC time constant set by the resistance of resistor 121 and capacitance between node 118 and node 103 provided by capacitor 125 and the gate capacitance of NMOS transistor 106. As the voltage at node 118 drops from the voltage of node 102 towards the voltage of node 103, NMOS transistor 106 will become increasingly resistive, until finally turning off as node 118 drops below the NMOS transistor threshold voltage at about 0.6V. The RC time constant for node 118 in on-time control circuit 107 may be adjusted so that NMOS transistor 106 conducts for a period of time at least equal to the maximum expected duration of an ESD event, here assumed to be 500–1000 ns.
In the circuit of FIG. 1, transient detection circuit 105 was designed to provide a high signal at node 112 until the end of any voltage ramp on node 102 up to the defined maximum ESD rise time of 60 ns. For example if the ESD event induces on node 102 a voltage ramp with a rise time of less than 60 ns (e.g. 30 ns), a proper high signal would be provided at node 112 until the end of the ramp. However, for ESD induced voltage ramps on node 102 with rise time in excess of the 60 ns maximum ESD rise time, transient detection circuit 105 does not function in a proper manner. This is illustrated in FIG. 3 which shows a simulated linear voltage ramp at node 102 from 0 to 4 V with a rise time of 80 ns. As can be seen in FIG. 3, node 110 crosses above the voltage switch point of inverter circuit 113, and node 112 switches low, at about 60 ns, before the end of the voltage ramp. Whenever this early time-out of transient detection circuit 105 occurs, node 118 will not be charged to the full peak voltage of node 102 seen at the end of the voltage ramp. This results in an undesirable increased resistance in the NMOS transistor 106, due to the fact that the gate of transistor 106 is not fully charged to the peak voltage of node 102 bias point. This is defined as weak turn on of NMOS transistor 106. In addition, the on time of NMOS transistor 106 will be reduced for two reasons. First, since the transient detection circuit 105 times out before the end of the voltage ramp, on-time control circuit 107 will begin timing out from this earlier point in time. Second, since the voltage at node 118 never reaches the peak voltage of node 102, the RC decay time to VSS for node 118 is reduced significantly. Therefore, in order to function optimally in an ESD event, transient detection circuit 105 should be designed to provide a high signal at node 112 until the end of any voltage ramp of node 102 up to the defined maximum ESD rise time of 60 ns. Since the transient detection circuit 105 is designed to function properly for ESD induced voltage ramp times only up to the required maximum ESD rise time (60 ns), any weak turn-on of NMOS transistor 106 for slower ramp times is unnecessary and undesirable.
One consideration for transient detection circuit 105 is that, while it properly detects an ESD event on node 102 with a rise time up to the maximum ESD rise time, it must also not turn on NMOS transistor 106 during normal IC operation. This undesirable turn on during normal operation is called false triggering. Due to the typical large size of NMOS transistor 106, any false triggering of this device would cause significant undesirable leakage from node 102 to node 103. Of greatest concern during normal operation is the ramp-up (power-up) of the VDD power supply rail as power is applied to the IC. The minimum power-up rise time is defined as the shortest possible rise time of the VDD supply during normal IC operation in the intended application. If the linear ramp to 4 V in 80 ns on node 102 (connected to a VDD rail) as shown in FIG. 3 were induced not by an ESD event, but during normal power-up of the IC, there may be false triggering by NMOS transistor 106. This is due to the fact that node 112 is above the voltage switch point of inverter circuit 113 for a significant portion of the rise time.
Because the voltage switch point of inverter circuit 113 is proportional to the instantaneous voltage at node 102, and because capacitor 111 is initially discharged, the voltage level at node 110 will always be below the voltage switch point of inverter circuit 113 at the beginning of a any positive voltage ramp at node 102. This occurs both during faster rise time ESD events and during slower rise time power-up of the VDD power supply during normal integrated circuit operation. With the transient detection circuit of FIG. 1, false triggering during normal VDD power-up can only be avoided if the output node 112 of transient detection circuit 105 switches to low before the voltage of node 102 reaches an NMOS threshold voltage to turn on clamp switch 106. This means that the minimum power-up rise time needs to be much larger than the maximum ESD rise time of transient detection circuit 105 in order to prevent false triggering of NMOS transistor 106. For the prior art transient detection circuit 105 of FIG. 1, the minimum power-up rise time to avoid false triggering of clamp switch 106 is about 240 ns. Note that this is four times larger than the 60 ns target maximum ESD rise time of the circuit. The minimum power-up rise time of 240 ns, as stated above, does not take into account variations in transient detection circuit 105 performance under worst case temperature and manufacturing conditions. These limitations may further increase the minimum power-up rise time limitations for the integrated circuit.
Therefore, with the circuit of FIG. 1, there exists a large gap in permissible rise times between the maximum ESD rise time and the minimum power-up rise time. With increasing VDD rise times, starting from the maximum ESD rise time, detection circuit 105 continues to trigger, but fires more and more weakly, until the minimum power-up rise time is reached. For longer rise times beyond this point, no false triggering is observed. As stated previously, ESD clamp circuit 101 needs only respond to ESD events with rise times up to 60 ns. Any false triggering of the clamp circuit for longer rise times is both unnecessary and undesirable. The primary concern with the false triggering exhibited by the prior art ESD clamp circuit 101 is that it sets a limit on the minimum power-up rise time during normal operation. This may cause problems in certain IC applications e.g. where the VDD power supply may ramp up during normal operation with very fast rise times in the range of 200–500 ns. While in the majority of IC applications the minimum power-up rise time is typically in the range from microseconds to milliseconds, there are applications where very fast power-up rise times can occur. For example, in some smartcard and printer applications, the IC may be inserted into a powered-up printed circuit board or socket, resulting in a very rapid ramp-up of the VDD power supply rail. For these applications, an ESD clamp circuit is needed which exhibits a much shorter gap between the maximum ESD rise time and the minimum power-up rise time, than that exhibited by prior art ESD clamp circuit 101.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.